DSpace Community:http://hdl.handle.net/10266/39142017-09-23T15:27:46Z2017-09-23T15:27:46ZImplementation of hebbian - LMS algorithmVartikaSakshi (Guide)http://hdl.handle.net/10266/48922017-09-22T22:21:03Z2017-09-22T00:00:00ZTitle: Implementation of hebbian - LMS algorithm
Authors: Vartika; Sakshi (Guide)
Abstract: In most of the engineered network systems, a set of operations interact with each other in
complex manners that can contain multiple types of relationships, depending on time and
include other types of complexities. Such network systems comprise multiple subsystems and
multiple layers of connectivity, and are generally called as multi-layer networks. There exist
multi-layer neural networks which are feed forward artificial neural network model that maps
sets of input data onto a set of appropriate outputs. it has multiple layers with each layer fully
connected to the next one. An artificial multi layers neural network contains three layers
broadly defined as input layer, hidden layer and output layer in the same order as written.
These network systems can be trained using both supervised and unsupervised algorithms.
The widely used supervised learning in these systems is LMS learning algorithm whereas the
unsupervised learning used is Hebbian learning. A form of LMS algorithm can be established
to achieve unsupervised learning. In this way LMS can be used to implement Hebbian
learning. This implementation of combined algorithms is called as Hebbian-LMS learning
algorithm. Combining the two algorithms creates a new unsupervised learning algorithm that
has application in practical engineering problems.
In this thesis, an artificial neural network is considered, whose hidden layer weights
are adjusted using Hebbian-LMS algorithm and the output layer is trained using the original
supervised LMS algorithm and the results are recorded for various datasets using this
approach as training algorithm in order to determine the feasibility of proposed algorithm in
networks required to solve some practical engineering problems.2017-09-22T00:00:00ZA Tensor-based Big Data Management Scheme for Dimensionality Reduction Problem in Smart Grid SystemsKaur, DevinderKumar, Neeraj (Guide)http://hdl.handle.net/10266/48912017-09-21T22:22:02Z2017-09-21T00:00:00ZTitle: A Tensor-based Big Data Management Scheme for Dimensionality Reduction Problem in Smart Grid Systems
Authors: Kaur, Devinder; Kumar, Neeraj (Guide)
Abstract: Smart grid (SG) is an integration of traditional power grid with advanced information and
communication infrastructure for bidirectional energy flow between grid and end users. A
huge amount of data is being generated by various smart devices deployed in SG systems.
Such a massive data generation from various smart devices in SG systems may generate
issues such as-congestion, and available bandwidth on the networking infrastructure
deployed between users and the grid. Hence, an efficient data transmission technique is required
for providing desired QoS to the end users in this environment. Generally, the data
generated by smart devices in SG has high dimensions in the form of multiple heterogeneous
attributes, values of which are changed with time. The high dimensions of data may
affect the performance of most of the designed solutions in this environment. Most of the
existing schemes reported in the literature have complex operations for data dimensionality
reduction problem which may deteriorate the performance of any implemented solution for
this problem. To address these challenges, in this paper, a tensor-based big data management
scheme is proposed for the problem of dimensionality reduction in big data generated
from various smart devices. In the proposed scheme, firstly the Frobenius norm is applied
on high-order tensors (used for data representation) to minimize the reconstruction error
of the reduced tensors. Then, an empirical probability-based control algorithm is designed
to estimate an optimal path to forward the reduced data using software-defined networks
(SDN) for minimization of the load and effective bandwidth utilization on the network infrastructure.
The proposed scheme minimizes the transmission delay occurred during the
movement of the dimensionally reduced data between different nodes. The efficacy of the
proposed scheme has been evaluated using extensive simulations carried out on the data
traces (power consumption of appliances in different smart homes) using ’R’ programming
and Matlab. The results obtained depict the effectiveness of the proposed scheme with
respect to the parameters such as- network delay, accuracy, and throughput.
Description: Master of Engineering -CSE2017-09-21T00:00:00ZInvestigations on Inter-Satellite Optical Wireless CommunicationKaur, RavneetSingh, Hardeep (Guide)http://hdl.handle.net/10266/48902017-09-21T22:22:21Z2017-09-21T00:00:00ZTitle: Investigations on Inter-Satellite Optical Wireless Communication
Authors: Kaur, Ravneet; Singh, Hardeep (Guide)
Abstract: The lightwave communication systems are capable of transmitting the signals at very high speeds. Distances up to thousands of kilometers are covered using LASERS and LED‟s as light sources. Inter-satellite link (ISL) has great significance for the global coverage with high rate switching and processing abilities. This concept extents lightwave communication technology into the space technology and the Inter-satellite Optical Wireless Communication. Inter-satellite optical wireless communication link exploits the intermixed features of two most powerful communication technologies Wireless and Optics to transmit data between two points using lasers. This technology is useful where fiber optic cable is impractical. Investigations have been carried out of the system for different linearly polarized modes such as LP00, LP01 and LP02 with return-to-zero (RZ), non-return-to-zero (NRZ) and compressed-spectrum-return-to-zero (CSRZ) modulation formats at varied data rates in terms of Q-factor and eye diagram. A comparison of the three modulation formats is formulated. As the performance of IsOWC is extremely affected by system data rate because Q-factor decreases with increase in the data rate. So results are taken at varied data rates of 5-50 Gbps. The projected setup is simulated for three diverse modulation formats RZ, NRZ and CSRZ using LPnm modes with input power of 0 dBm and transmission distance of 1000 km at operating wavelength of 1550 nm. It has been observed that for any LPnm mode Q-factor increases with increase in Tx/Rx aperture diameter. Results demonstrate successful transmission of LP modes through IsOWC link.
Description: Master of Engineering -Wireless Communication2017-09-21T00:00:00ZImplementation of Sequential Decimal MultiplierGupta, SonalShakshi (Guide)http://hdl.handle.net/10266/48832017-09-19T22:20:46Z2017-09-19T00:00:00ZTitle: Implementation of Sequential Decimal Multiplier
Authors: Gupta, Sonal; Shakshi (Guide)
Abstract: Multiplication is the most important operation among all the four arithmetic operations during the last decade in various fields which is in the top list of research. Decimal multiplication is gaining very high popularity in recent years in the fields like analysis of finance, banking, income tax department, insurance and many more such fields. The hardware implementation of this has become a very important and interesting topic of research. There are a number of multipliers such as serial multiplier, parallel decimal multiplier, booth multiplier, Wallace tree multiplier, combinational decimal multiplier, sequential decimal multiplier, array multiplier and sequential multiplier. Each multiplier has its own advantages and disadvantages. Among all these multipliers, the implementation of parallel decimal multiplier is considered to be the hardest because of its high cost of area. The processor industries have implemented a new version of multipliers which is sequential decimal multipliers so as to reduce this high implementation cost. The problem with this sequential decimal multiplier is its high latency. In the reported work, the focus is to generate a sequential decimal multiplier with lowest possible area, delay and power consumption. The BCD-8421 coding mechanism is used to generate easy multiples and partial products.
Description: Master of Technology -VLSI Design2017-09-19T00:00:00Z