Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/2346
Title: Impact of Voltage Scaled Repeaters on Delay and Power Dissipation of CNT and Copper Interconnects
Authors: Saini, Sandeep
Sandha, Karmjit Singh (Guide)
Keywords: Interconnects
repeaters
Issue Date: 23-Aug-2013
Abstract: Abstract In VLSI circuits, at sub-micron level, the resistivity of copper increases due to several factors due to which delay and power dissipation increase. This degrades the system performance of the circuits.Carbon nanotubes (CNTs) have provided an attractive solution over Copper at deep sub-micron level very large scale integration (VLSI) technologies. Propagation delay and power dissipation are the major design constraints in very large scale integration (VLSI) circuits. Long interconnections between devices in VLSI circuits also give rise to power dissipation and propagation delay as it increases RC time constant. Repeater insertion is the answer to these challenges. This thesis presents an analysis of propagation delay and effect of repeater insertion on propagation delay for both CNT and Cu interconnects. It has been observed that CNT interconnects have lower propagation delay than the Copper interconnects. Also, propagation delay reduces as we increase the number of repeaters. The above trends are studied with different technology nodes viz. 32nm and 22 nm. In addition, this work deals with the effect of voltage scalingon propagation delay and power dissipationin repeaters loaded long interconnect used in VLSI circuits. It has been observed that the use of voltage scaling reduces the propagation delay. Use of voltage scaling results in decrease in number of optimum repeaters required. Power dissipation increases as voltage is scaled down. Thus, the down scaling of voltage inthe inserted repeaters in aninterconnect can be useful for the cases wherecontrol of power dissipation is a stern requirement. The results for the propagation delay and power dissipation have been obtained using SPICE simulations. The simulation results for 32 nmand 22 nm CMOS technologies have been given for both CNT and Copper interconnects.
Description: ME, ECE
URI: http://hdl.handle.net/10266/2346
Appears in Collections:Masters Theses@ECED

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