Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/4385
Title: Study the Temperature-Dependent Analytical Time Domain Delay Model for Performance Optimization of Single-Walled Carbon Nanotube (SWCNT) Bundle Based VLSI Interconnects
Authors: Gupta, Anu
Rai, Mayank Kumar (Guide)
Keywords: CARBON NANOTUBE
Delay
Interconnects
Issue Date: 25-Oct-2016
Abstract: As the technology is advancing, the device and interconnect dimensions are scaling down from submicron to deep submicron (DSM) regime. This leads to increase in the density of integrated circuits and hence increase in length of the interconnect. Smaller widths and longer lengths cause decay in the conductive properties of copper interconnects and give rise to reliability issues. Additionally, progressive scaling leads to increase in operating temperature of the integrated circuit and thus the thermal issues are also a major concern. Carbon nanotubes (CNTs) due to their extraordinary mechanical strength and thermal stability have spurred a lot of interest in the research of their use as the next generation VLSI interconnects. This thesis presents a temperature-dependent analytical model to extract the transient response of the far end of the Single-walled carbon nanotube (SWCNT) bundle interconnects. The overall logic stage delay of a CMOS driven SWCNT bundle interconnect is estimated. The driving transistor is represented by alpha power law model and all the operating regions of transistor are taken into account. The gate delay is obtained by modeling the driving point admittance at the gate output using an effective capacitance. The effective capacitance model takes into consideration the resistance shielding effect and is also compatible with the empirically derived equations. The gate delay obtained analytically for both slow and fast input ramp is in good agreement with the SPICE results. The interconnect delay is estimated by the numerical convolution of gate output and two-pole approximated transfer function of distributed interconnect line. The overall logic delay from analytical model is within 7.9% of the SPICE computed delay. The voltage waveforms at both near end and far end of the interconnect are compared with SPICE simulations. It is observed that the results match quite closely. A comparative analysis in terms of delay performance between SWCNT bundle interconnects with resistance obtained using temperature independent model and thermally aware model is carried out. The simulations are done at 22nm technology node at 300K temperature for lengths varying from 200 m to 1000 m. An average improvement of 18.18% is observed in delay estimated using thermally aware model iv over temperature dependent model of resistance. A similar analysis is performed to compare the delay of SWCNT bundle interconnect with that of copper interconnect, at 22 nm technology node, with temperatures varying from 300K to 500K and lengths varying from 200 m to 1000 m. The simulation results reveal that the delay of copper interconnects is larger than that of SWCNT bundle interconnects for the entire range of length and temperature. This is due to the dominance of line resistance over capacitance and inductance that determines the propagation delay of interconnect, and copper has higher line resistance as compared to SWCNT bundle.
Description: MTech Thesis
URI: http://hdl.handle.net/10266/4385
Appears in Collections:Masters Theses@ECED

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