Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/4819
Title: Efficient Design of Iterative Decoding Algorithm and Architecture for Channel Coding
Authors: Pasricha, Shivani
Sharma, Sanjay (Guide)
Keywords: turbo, LDPC, Sliding window, Parallel window
Issue Date: 3-Sep-2017
Abstract: The demand for information exchange is ever increasing for most of the communication models. The communication systems are designed and developed for transmitting the information from source to a remote destination. The major purpose for designing the communication system is the accurate and error-free transmission of information between source and destination. The symbols produced by the information source are given to the source encoder. The source encoder assigns code words to the symbols. For each distinct symbol, there is a unique codeword.Errors may be introduced while transmitting these binary sequences over the channel due to noise and interference.At the receiver end, some sort of decoder is used to perform the reverse operation of source encoder. The channel decoder provides decoded output which is converted into a sequence of symbols. Errors may be introduced while transmitting the binary sequences over the channel due to noise and interference. Channel coding is done to avoid these types of errors. Some redundant binary bits are added to the input sequence by the channel encoder according to some pre-defined logic. The channel decoder at the receiver end reconstructs error-free accurate bit sequence, thus reducing the effects of channel noise and distortion. The error-control strategies are used by the channel encoder and decoder at the receiver to reduce the errors in the received signals. For example, forward error correction (FEC) or automatic repeat request (ARQ) techniques are used to correct errors and increase the reliability of the received signals. This thesis discusses the error control aspects of a communication system, in particular, the error-correcting Turbo codes and LDPC code. Turbo codes, introduced in 1993, are designed by combining two or more relatively simple component codes to achieve a large coding gain. The information in turbo codes is encoded twice but in a different order. Recently, focus has turned on iterative decoding of turbo codes using “soft-in/soft-out” decoding scheme. The decoding of a complex and long code is ii broken up in steps and the decoding steps are interlinked so that the information is not lost while decoding. This thesis presents realization of simplified VLSI architectures for turbo decoders using QPP and S-random Interleaver and also evaluates different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. The most significant concern for Turbo codes is to efficiently implement a turbo decoder. A simplified and efficient implementation of a turbo decoder using field programmable gate array (FPGA) technology has been presented in this thesis. An integer-based Turbo decoder has been designed based on the standard 2‟s complement number system by analyzing issues of dynamic range and truncation effect. The integer-based Turbo decoder has been efficiently implemented by modifying the algorithm, applying integer arithmetic, and managing the compact hardware. The Max-Log-MAP decoding algorithm is used to modify the branch metric by weighing a-priori value for significantly improving the BER. The Turbo decoder generates 7-bit soft-decisions by using 8-level integer inputs, determines metrics on integers, and avoids complex floating point or fixed-point arithmetic. The memory address is manipulated to eliminate delay associated with interleaving and de-interleaving and to provide improvement in the throughput. Additionally, the Turbo decoder is implemented in a single-decoder structure by efficiently using the memory and logic cells. Verilog hardware description language has been used to describe the Turbo decoder. XCV300E FPGA chip has been used to implement the Turbo decoder. The design used approximately 28 RAM blocks out of 48 total RAM blocks and 3447 cells out of 6912 logic cells in the device. No additional external components were required in the design. Further, the power consumption of the designed device during normal operation was approximately 695 mW. FPGA implementation of turbo decoder with 8 iterations can operate at a frequency of and give throughput of more than 1 Mbps. iii Different VLSI architectures have also been analyzed for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. The performance of SWSISO MAP (maximum a posteriori)turbo decoder, standard SISO MAP turbo decoder, and PW SISO MAP turbo decoder have been analyzed on the basis of data flow graphs. Two different variants of quadratic permutation polynomial (QPP) interleaver have been proposed for simplifying complexity of “mod” operator implementation and providing best trade-off between power dissipation, delay, and area. Also, a turbo decoder with one variant of QPP interleaver has been implemented and analyzed. A novel technique for optimizing the area has been proposed to reduce the number of interleavers required for implementing a parallel window turbo decoder using multi-port memory. The circuit-level retiming and pipelining techniques have been used to improve the throughput without increasing the area complexity. The proposed decoders have been simulated using ModelSim 10.1 student edition and synthesized using Synopsys Design Compiler tool version D-2010.03-SP1. The synthesis results show an increased throughput of advanced decoders in comparison with the standard decoder, but at the same time, there is an increase in power and area requiremente. Considerable amount of area can be saved by applying an improved interleaving technique to PW decoders saves. Simulation results corresponding to throughput and latency for different architectures of turbo decoders have been shown in the work. Interleaving is normally used in digital communication and storage systems to improve the performance of forward error correcting codes. For turbo codes, an interleaver is an essential constituent and its appropriate design is decisive for superior performance. Quadratic permutation polynomial (QPP) interleaver is a contention free interleaver that is appropriate for parallel turbo decoder realization. A new interleaver design, an alternative of QPP interleaver of turbo codes, has been suggested which permutes a series of bits with the identical statistical properties as a conformist QPP interleaver and performs superior than the iv predictable QPP. New proposed architecture has been simulated and synthesized using Xilinx and HDL Designer tools. Very large scale amalgamation of architecture for the proposed interleaver has been investigated in terms of area, delay and power dissipation. Thermal power indulgence and device operation has been computed for the novel plan using QuartusII (32-bit) tool. Also, a contrast among the proposed alternative of QPP interleaver and the conformist QPP interleaver has been presented. Low-Density parity-check (LDPC) codes were proposed by Robert Gallager in 1963 as error correction codes. These codes allow communicating over the noisy channels near the Shannon capacity limits. LDPC codes were overlooked for thirty years due to their high computational complexity for hardware technology at that time. Then LDPC codes were rediscovered by MacKay and Neal in 1990. LDPC codes are represented using the matrices or with a connected set of graph called as tanner graph. Tanner graph is used for mapping a parity check matrix with the nodes. In the tanner graph, the number of columns in the matrix is equal to number of variable nodes and the number of rows is equal to number of check nodes. Message-passing decoding iterative algorithms are used at the decoder end of LDPC codes. The messages are exchanged between the variable nodes and the check nodes in discrete time steps of the message-passing decoding iterative algorithms. This process is continued till a specified number of iterations are processed. Several message-passing decoding algorithms have been proposed, among which the algorithm which provides the best performance is belief propagation (BP) algorithm. In this thesis LDPC decoder has been realized using partially parallel decoder architecture and simplified soft-decision log-belief propagation algorithm.The realized architecture possesses high speed and greatly reduces the routing and check node complexity of the decoder. This work presents introduction to LDPC codes and its various decoding algorithms v followed by realization of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family. The thesis has been organized in six chapters. Chapter 1 presents the introduction, motivation, formulation of problem, objectives of the thesis, and organization of the thesis. Chapter 2 deals with the preface to turbo codes and iterative decoding algorithms employed at decoder end of telecommunication system. The chapter also talks about FPGA implementation of the basic and proficient turbo decoder. Chapter 3 evaluates various VLSI designs for 3GPP LTE/LTE advanced turbo decoders for comparison in terms of output and area constraints. Chapter 4 discussesa new proposed interleaver blueprint which is an alternative of QPP interleaver, which permutes a series of bits with identical statistical allocation as a conformist QPP interleaver and executes better than conformist interleaver for turbo codes. Chapter 5 presents preamble to LDPC codes and its different decoding algorithms followed by the understanding of LDPC decoder with the help of basic message passing algorithm technique and to some extent parallel decoder architecture design. Basic message passing algorithm significantly diminishes routing and checks node complication of decoder and also provides comparison among the low decoding complexity and performance of decoder. vi Finally, Chapter 6 concludes the research work. Further, a brief description about the future work/scope will be given as a motivational seed for further research work.
URI: http://hdl.handle.net/10266/4819
Appears in Collections:Doctoral Theses@ECED

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